mirror of https://github.com/zachjs/sv2v.git
13 lines
216 B
Systemverilog
13 lines
216 B
Systemverilog
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interface I;
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logic [3:0] x;
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endinterface
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module top;
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I i();
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if (1) begin : blk
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typedef logic I;
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var I i;
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assign i = 0;
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end
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initial $display("%b %b", i.x, blk.i);
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endmodule
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