mirror of https://github.com/zachjs/sv2v.git
10 lines
238 B
Systemverilog
10 lines
238 B
Systemverilog
|
// pattern: port intf has type Interface1, but the binding intf2 has type Interface2
|
||
|
|
`include "interface_mismatch.svh"
|
||
|
|
module Module(intf);
|
||
|
|
Interface1 intf;
|
||
|
|
endmodule
|
||
|
|
module top;
|
||
|
|
Interface2 intf2();
|
||
|
|
Module m(intf2);
|
||
|
|
endmodule
|