mirror of https://github.com/zachjs/sv2v.git
19 lines
359 B
Systemverilog
19 lines
359 B
Systemverilog
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module example(
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input wire [7:0] inp,
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output wire [7:0] out
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);
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assign out = ~inp;
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endmodule
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module top;
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reg arr1 [7:0][1:0];
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reg arr2 [7:0][1:0][1:0];
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wire [7:0] out1, out2;
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example e1(arr1[0], out1);
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example e2(arr2[0][0], out2);
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initial begin
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#1 arr1[0] = 8'hAD;
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#1 arr2[0][0] = 8'h42;
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end
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endmodule
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