mirror of https://github.com/zachjs/sv2v.git
33 lines
639 B
Systemverilog
33 lines
639 B
Systemverilog
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interface InterfaceA;
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logic x;
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modport M(input x);
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endinterface
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interface InterfaceB;
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logic y;
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modport N(input y);
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endinterface
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module ModuleA(modport_a);
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InterfaceA modport_a;
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initial $display("ModuleA %b", modport_a.x);
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endmodule
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module ModuleB(modport_b);
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InterfaceB modport_b;
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InterfaceA interface_a();
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ModuleA module_a(interface_a.M);
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initial $display("ModuleB %b", modport_b.y);
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assign interface_a.x = 0;
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endmodule
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module ModuleC;
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InterfaceB interface_b();
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ModuleB module_b(interface_b.N);
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assign interface_b.y = 1;
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endmodule
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module top;
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ModuleC module_c();
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endmodule
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