mirror of
https://github.com/zachjs/sv2v.git
synced 2026-09-06 09:28:58 +02:00
6 lines
80 B
Verilog
6 lines
80 B
Verilog
|
module top;
|
||
|
|
reg [5:0] a;
|
||
|
|
wire [5:0] b;
|
||
|
|
always @(*) a = b;
|
||
|
|
endmodule
|