mirror of https://github.com/zachjs/sv2v.git
115 lines
3.4 KiB
Systemverilog
115 lines
3.4 KiB
Systemverilog
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module top;
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function parity;
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input [3:0] arr;
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parity = arr[2] ^ arr[2] ^ arr[1] ^ arr[0];
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endfunction
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task loop;
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input [3:0] arr;
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begin
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arr = 4'b0000;
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repeat (2**4) begin
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$display("%04b -> %d", arr, parity(arr));
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arr += 1;
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end
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end
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endtask
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task dump;
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begin : dump_block
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integer i;
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for (i = 0; i < 7; i += 1) begin
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$display("arr[%1d] = %04b", i, arr[i]);
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end
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end
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endtask
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task reinterpret;
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input [3:0][6:0] arr;
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begin : reinterpret_block
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integer i;
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for (i = 0; i < 4; i += 1) begin
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$display("arr'[%1d] = %07b", i, arr[i]);
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end
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end
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endtask
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logic [6:0][3:0] arr;
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initial arr = 28'h9fba7d;
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integer i;
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initial begin
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for (i = 0; i < 7; i += 1) begin
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loop(arr[i]);
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dump();
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reinterpret(arr);
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end
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end
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logic [1:0] foolA;
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initial begin
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foolA = 2'b10;
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foolAer(4'b1001);
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$display("initalA: $bits(foolA): ", $bits(foolA ));
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$display("initalA: $bits(foolA[0]): ", $bits(foolA[0]));
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$display("initalA: foolA[0]: ", foolA[0]);
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$display("initalA: foolA[1]: ", foolA[1]);
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end
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task foolAer;
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input [1:0][1:0] foolA;
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begin
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$display("foolAer: $bits(foolA): ", $bits(foolA ));
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$display("foolAer: $bits(foolA[0]): ", $bits(foolA[0] ));
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$display("foolAer: $bits(foolA[0][0]): ", $bits(foolA[0][0]));
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$display("foolAer: foolA[0][0]: ", foolA[0][0]);
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$display("foolAer: foolA[0][1]: ", foolA[0][1]);
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$display("foolAer: foolA[1][0]: ", foolA[1][0]);
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$display("foolAer: foolA[1][1]: ", foolA[1][1]);
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end
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endtask
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task foolBer;
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input [1:0][1:0] foolB;
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begin
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$display("foolBer: $bits(foolB): ", $bits(foolB ));
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$display("foolBer: $bits(foolB[0]): ", $bits(foolB[0] ));
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$display("foolBer: $bits(foolB[0][0]): ", $bits(foolB[0][0]));
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$display("foolBer: foolB[0][0]: ", foolB[0][0]);
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$display("foolBer: foolB[0][1]: ", foolB[0][1]);
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$display("foolBer: foolB[1][0]: ", foolB[1][0]);
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$display("foolBer: foolB[1][1]: ", foolB[1][1]);
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end
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endtask
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logic [1:0] foolB;
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initial begin
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foolB = 2'b10;
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foolBer(4'b1001);
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$display("initalB: $bits(foolB): ", $bits(foolB ));
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$display("initalB: $bits(foolB[0]): ", $bits(foolB[0]));
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$display("initalB: foolB[0]: ", foolB[0]);
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$display("initalB: foolB[1]: ", foolB[1]);
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end
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task magic;
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begin
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begin : magic_block
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logic [1:0][1:0] magic_arr;
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magic_arr = 4'b1001;
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$display("$bits(magic_arr): ", $bits(magic_arr ));
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$display("$bits(magic_arr[0]): ", $bits(magic_arr[0] ));
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$display("$bits(magic_arr[0][0]): ", $bits(magic_arr[0][0]));
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$display("magic_arr[0][0]: ", magic_arr[0][0]);
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$display("magic_arr[0][1]: ", magic_arr[0][1]);
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$display("magic_arr[1][0]: ", magic_arr[1][0]);
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$display("magic_arr[1][1]: ", magic_arr[1][1]);
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end
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end
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endtask
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initial magic();
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endmodule
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