mirror of https://github.com/zachjs/sv2v.git
13 lines
230 B
Verilog
13 lines
230 B
Verilog
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module top;
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reg [1:0] a;
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wire b;
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Example example(a, b);
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initial begin
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$monitor("%2d %b %b", $time, a, b);
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#1;
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#1; a[0] = 1;
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#1; a[1] = 1;
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#1; a[0] = 1'sbx;
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end
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endmodule
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