luke
/
sv2v
mirror of https://github.com/zachjs/sv2v.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
sv2v/test/basic/package_constrain_tb.v

4 lines
47 B
Verilog
Raw Normal View History

package conversion overhaul - full import and export support - simplify AST representation of import and export - allow package-scoped identifiers invoked as subroutines - use scoped name resolution for identifiers in packages - merge package item nesting conversion into package conversion - fix handling of colliding enum items in separate modules - fix visiting enum item exprs in types
2021-01-24 00:50:06 +01:00
module top;
Example e(5'b00000);
endmodule