mirror of https://github.com/zachjs/sv2v.git
13 lines
238 B
Verilog
13 lines
238 B
Verilog
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module top;
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reg signed x;
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initial x = 1;
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parameter ONE = 1;
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initial begin : blk
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reg signed [4:0] y;
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y = x;
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$display("%b", y);
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$display("%b", y);
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$display("%b", y);
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end
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endmodule
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