mirror of https://github.com/zachjs/sv2v.git
9 lines
170 B
Verilog
9 lines
170 B
Verilog
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module top;
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initial $display("%b", 2'b11);
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generate
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if (1) begin : blk2
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initial $display("%b", 3'b111);
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end
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endgenerate
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endmodule
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