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14 lines
335 B
Verilog
14 lines
335 B
Verilog
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module Unpacker(in, select, a, b, c);
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parameter WIDTH = 8;
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input wire [WIDTH-1:0][6:0] in;
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input wire [$clog2(WIDTH)-1:0] select;
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output wire a;
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output wire [3:0] b;
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output wire [1:0] c;
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wire [6:0] p;
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assign p = in[select];
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assign a = p[6:6];
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assign b = p[5:2];
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assign c = p[1:0];
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endmodule
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