sv2v/test/basic/interface_infer.v

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Verilog
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module Module(input wire x);
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initial $display("Module %d", x);
endmodule
module top;
wire i_x;
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localparam SOME_VAL = 3;
initial $display("Interface %d %d", i_x, SOME_VAL);
Module m(.x(i_x));
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generate
genvar g;
for (g = 0; g < 5; g = g + 1) begin
initial $display(g);
end
for (g = 10; g < 15; g = g + 1) begin
initial $display(g);
end
endgenerate
endmodule