mirror of https://github.com/zachjs/sv2v.git
8 lines
155 B
Systemverilog
8 lines
155 B
Systemverilog
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module top;
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logic [3:0] arr;
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always_comb
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for (int unsigned i = 0; i < 4; i++)
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arr[i] = i;
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initial $display(arr);
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endmodule
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