mirror of https://github.com/zachjs/sv2v.git
27 lines
747 B
Haskell
27 lines
747 B
Haskell
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for `unsigned` types.
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-
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- Verilog-2005 makes `reg`, `wire`, etc. unsigned by default. Further, it does
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- not have the `unsigned` keyword. This conversion ensures we either mark a
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- data type as `signed` or leave the signing unspecified.
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-}
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module Convert.Unsigned (convert) where
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: [AST] -> [AST]
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convert =
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map $
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traverseDescriptions $
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traverseModuleItems $
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traverseTypes convertType
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convertType :: Type -> Type
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convertType (IntegerVector t Unsigned rs) = IntegerVector t Unspecified rs
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convertType (Net t Unsigned rs) = Net t Unspecified rs
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convertType other = other
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