mirror of https://github.com/zachjs/sv2v.git
9 lines
192 B
Verilog
9 lines
192 B
Verilog
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module top;
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initial begin
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$display($signed(4294967295));
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$display($unsigned(4294967295));
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$display($signed(-1));
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$display($unsigned(-1));
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end
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endmodule
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