mirror of https://github.com/zachjs/sv2v.git
12 lines
233 B
Verilog
12 lines
233 B
Verilog
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module top;
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localparam [2:0] AccessAck = 3'd0;
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wire [2:0] test;
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always @(*) begin
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case (test)
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AccessAck: $display("Ack");
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default : $display("default");
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endcase
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end
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endmodule
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