mirror of https://github.com/zachjs/sv2v.git
16 lines
316 B
Verilog
16 lines
316 B
Verilog
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`define DUMP(id) #1 $display(`"id: %b`", arr);
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module top;
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parameter A = 5;
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reg [A-1:0] arr;
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initial arr = 1'sb1;
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initial `DUMP(0)
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if (1) begin : blk
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localparam A = 10;
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initial `DUMP(1)
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end
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initial begin : foo
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localparam A = 10;
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`DUMP(2)
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end
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endmodule
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