mirror of https://github.com/zachjs/sv2v.git
13 lines
288 B
Systemverilog
13 lines
288 B
Systemverilog
|
module Module(input clock, input clear, input data);
|
||
|
|
logic x, y;
|
||
|
|
assign y = data;
|
||
|
|
assign x = y;
|
||
|
|
assert property (
|
||
|
|
@(posedge clock) disable iff(clear) x == y
|
||
|
|
);
|
||
|
|
task hello;
|
||
|
|
$display("Hello!");
|
||
|
|
assert property (x == y);
|
||
|
|
endtask
|
||
|
|
endmodule
|