mirror of https://github.com/zachjs/sv2v.git
12 lines
261 B
Systemverilog
12 lines
261 B
Systemverilog
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// pattern: declaration dst uses interface name I where a type name is expected
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// location: interface_name_func.sv:5:12
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interface I;
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logic [3:0] x;
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task t(I dst, I src);
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dst.x <= src.x;
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endtask
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endinterface
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module top;
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I i();
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endmodule
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