mirror of https://github.com/zachjs/sv2v.git
5 lines
118 B
Systemverilog
5 lines
118 B
Systemverilog
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module top;
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wire a, b, c, d, e;
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assign a = b ? (* ternary *) ~^ (* unary *) c : d & (* binary *) e;
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endmodule
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