mirror of https://github.com/zachjs/sv2v.git
13 lines
266 B
Verilog
13 lines
266 B
Verilog
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module top;
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wire [3:0] i_x;
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reg [1:0] i_w;
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assign i_x = 4'b1001;
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initial i_w = 2'b10;
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initial begin
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$display("%b", i_x[3]);
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$display("%b", i_x[2]);
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$display("%b", i_x[1]);
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$display("%b", i_x[0]);
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end
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endmodule
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