mirror of https://github.com/zachjs/sv2v.git
14 lines
250 B
Verilog
14 lines
250 B
Verilog
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module top;
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wire x, f_x;
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wire f_a_x, f_b_x;
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assign x = 1;
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assign f_x = x;
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assign f_a_x = x;
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assign f_b_x = ~x;
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initial begin
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$display("bar got %b", f_a_x);
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$display("bar got %b", f_b_x);
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end
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endmodule
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