mirror of https://github.com/zachjs/sv2v.git
44 lines
795 B
Systemverilog
44 lines
795 B
Systemverilog
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interface bundle;
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logic [1:0] index;
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logic clock;
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logic [3:0] inp;
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logic out;
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endinterface
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module rotator(bundle b);
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initial b.index = 0;
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always @(posedge b.clock)
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b.index <= b.index + 1;
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endmodule
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module setter(bundle b);
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initial b.inp = '1;
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always @(posedge b.clock)
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b.inp[b.index] <= b.out;
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endmodule
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module reducer(bundle b);
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assign b.out = ^b.inp;
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endmodule
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module clocker(bundle b);
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initial begin
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b.clock <= 0;
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forever
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#5 b.clock <= ~b.clock;
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end
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endmodule
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module top;
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bundle b();
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rotator rot(b);
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setter set(b);
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reducer red(b);
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clocker clk(b);
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initial begin
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$monitor("%b %b %b %b", b.index, b.clock, b.inp, b.out);
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#100;
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$finish;
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end
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endmodule
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