mirror of https://github.com/zachjs/sv2v.git
11 lines
205 B
Systemverilog
11 lines
205 B
Systemverilog
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`define TEST(value) \
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logic [63:0] val_``value = 'value; \
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initial $display(`"'value -> %b %b", val_``value, 'value);
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module top;
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`TEST(1);
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`TEST(0);
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`TEST(x);
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`TEST(z);
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endmodule
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