mirror of https://github.com/zachjs/sv2v.git
56 lines
1.1 KiB
Systemverilog
56 lines
1.1 KiB
Systemverilog
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module top;
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initial begin
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logic x;
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$display($bits(x));
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begin
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logic [0:$bits(x)] x;
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$display($bits(x));
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begin
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logic [0:$bits(x)] x;
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$display($bits(x));
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end
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end
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end
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initial begin
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logic x;
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$display($bits(type(x)));
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begin
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logic [0:$bits(type(x))] x;
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$display($bits(type(x)));
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begin
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logic [0:$bits(type(x))] x;
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$display($bits(type(x)));
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end
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end
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end
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initial begin
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logic x;
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$display($bits(x));
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begin
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logic [0:$bits(type(x))] x;
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$display($bits(x));
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begin
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logic [0:$bits(type(x))] x;
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$display($bits(x));
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end
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end
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end
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initial begin
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logic x;
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$display($bits(type(x)));
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begin
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logic [0:$bits(x)] x;
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$display($bits(type(x)));
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begin
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logic [0:$bits(x)] x;
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$display($bits(type(x)));
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end
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end
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end
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endmodule
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