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13 lines
245 B
Systemverilog
13 lines
245 B
Systemverilog
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package foo_pkg;
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typedef enum logic [2:0] {
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AccessAck = 3'd0,
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AccessAckData = 3'd1
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} inp_t;
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endpackage
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module top;
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foo_pkg::inp_t test;
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assign test = foo_pkg::AccessAck;
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initial $display(test);
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endmodule
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