mirror of https://github.com/zachjs/sv2v.git
18 lines
334 B
Systemverilog
18 lines
334 B
Systemverilog
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module top;
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function f;
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input integer z;
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input integer a;
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$display(z, a);
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return z + a;
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endfunction
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task t;
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input integer z;
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input integer a;
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$display(z, a);
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endtask
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initial begin
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$display(f(.a(3), .z(7)));
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t(.a(5), .z(9));
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end
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endmodule
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