mirror of https://github.com/zachjs/sv2v.git
24 lines
497 B
Systemverilog
24 lines
497 B
Systemverilog
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interface Interface;
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integer x;
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endinterface
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module Single(intf);
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Interface intf;
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initial #1 $display("Single %0d", intf.x);
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endmodule
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module Group(intfs);
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parameter WIDTH = 1;
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Interface intfs [WIDTH];
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initial $display("Group %0d", WIDTH);
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for (genvar i = 0; i < WIDTH; ++i)
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Single s(intfs[i]);
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endmodule
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module top;
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Interface intfs[8]();
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for (genvar i = 0; i < 8; ++i)
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initial intfs[i].x = i ** 3;
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Group #(.WIDTH(8)) g(intfs);
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endmodule
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