mirror of https://github.com/zachjs/sv2v.git
13 lines
238 B
Systemverilog
13 lines
238 B
Systemverilog
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module Example(flag, out);
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typedef struct packed {
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logic a, b;
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} T;
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output T out;
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input logic flag;
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assign out =
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flag
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? '{ a: 1'b1, b: 1'b0 }
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: '{ a: 1'b1, b: 1'b1 }
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;
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endmodule
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