mirror of https://github.com/zachjs/sv2v.git
6 lines
126 B
Verilog
6 lines
126 B
Verilog
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module top;
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localparam X = NUM;
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localparam [63:0] Y = X;
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initial $display("%0d %b %b", $bits(X), X, Y);
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endmodule
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