mirror of https://github.com/zachjs/sv2v.git
8 lines
133 B
Systemverilog
8 lines
133 B
Systemverilog
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module mod(output logic out);
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assign out = 1;
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endmodule
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module top;
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logic x;
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mod m((* foo *)(* bar *).out(x));
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endmodule
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