mirror of https://github.com/zachjs/sv2v.git
13 lines
232 B
Verilog
13 lines
232 B
Verilog
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module top;
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parameter P = 3;
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wire [P + 1:0] x;
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wire [2 * P + 4:0] y, z;
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assign y = {x, x};
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generate
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if (1) begin : blk
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wire x;
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end
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endgenerate
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assign z = {blk.x, x};
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endmodule
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