mirror of https://github.com/zachjs/sv2v.git
17 lines
347 B
Systemverilog
17 lines
347 B
Systemverilog
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module top;
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function automatic integer incr;
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input integer inp;
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return inp + 1;
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endfunction
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parameter P = 3;
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logic [incr(P):0] x;
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logic [$bits(x) * 2:0] y, z;
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if (1) begin
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assign top.y = {top.x, x};
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end
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if (1) begin : blk
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wire x;
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assign z = {blk.x, top.x};
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end
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endmodule
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