mirror of https://github.com/zachjs/sv2v.git
9 lines
151 B
Verilog
9 lines
151 B
Verilog
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module top;
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`include "always_spin.vh"
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wire [Z - 1:0] foo;
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wire flag;
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reg bar;
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always @*
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bar = foo[Z - 1] & flag;
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endmodule
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