mirror of https://github.com/zachjs/sv2v.git
15 lines
212 B
Systemverilog
15 lines
212 B
Systemverilog
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module top;
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logic x;
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always_comb
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x = 0;
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`include "always_comb.vh"
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`TEST(_comb, 1)
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`TEST(_comb, 2)
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`TEST(@*, 3)
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`TEST(@*, 4)
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initial x1 = 0;
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initial x3 = 0;
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endmodule
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