mirror of https://github.com/zachjs/sv2v.git
11 lines
190 B
Verilog
11 lines
190 B
Verilog
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module top;
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reg a, b, c;
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(* test *) always @(posedge a)
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c <= b;
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(* test *) always @*
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if (c)
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b <= 1;
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(* test *) always @*
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a = b;
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endmodule
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