mirror of
https://github.com/zachjs/sv2v.git
synced 2026-09-07 11:51:28 +02:00
8 lines
112 B
Verilog
8 lines
112 B
Verilog
|
module top;
|
||
|
|
reg [1:0] w;
|
||
|
|
initial begin
|
||
|
|
w <= 2'b00;
|
||
|
|
$display("%b", w);
|
||
|
|
end
|
||
|
|
endmodule
|