mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 01:18:10 +02:00
5 lines
63 B
Verilog
5 lines
63 B
Verilog
|
module top;
|
||
|
|
wire x = 1;
|
||
|
|
initial $display(x);
|
||
|
|
endmodule
|