mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-31 09:44:27 +02:00
7 lines
97 B
Verilog
7 lines
97 B
Verilog
|
module top;
|
||
|
|
task foo;
|
||
|
|
$display("foo called");
|
||
|
|
endtask
|
||
|
|
initial foo;
|
||
|
|
endmodule
|