mirror of https://github.com/zachjs/sv2v.git
11 lines
170 B
Verilog
11 lines
170 B
Verilog
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module top;
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reg inp;
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wire out;
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Example e(inp, out);
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initial
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repeat(5) begin
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#1 inp = 0;
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#1 inp = 1;
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end
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endmodule
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