mirror of https://github.com/zachjs/sv2v.git
22 lines
297 B
Verilog
22 lines
297 B
Verilog
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`default_nettype none
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// Verilog unwraps the typedef
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module Example(
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input wire [3:0] data_in,
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output wire [31:0] data_out
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);
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reg [31:0] word;
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always @* begin
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// This is the repeat operator
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word = {8{data_in}};
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end
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assign data_out = word;
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endmodule
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