mirror of https://github.com/zachjs/sv2v.git
24 lines
372 B
Verilog
24 lines
372 B
Verilog
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`default_nettype none
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module top;
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wire [3:0] a;
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wire [31:0] result;
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Example dut(
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.a(a),
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.all(result)
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);
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reg [4:0] _a;
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assign a = _a[3:0];
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initial begin
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$monitor($time, "a: %b result: %h", a, result);
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for (_a = 0; _a < 5'hf; _a = _a + 1) begin
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#10;
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end
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$finish;
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end
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endmodule
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