mirror of https://github.com/zachjs/sv2v.git
59 lines
1.2 KiB
Verilog
59 lines
1.2 KiB
Verilog
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// interface CacheSetInterface(
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// input logic [7:0] request,
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// output logic [7:0] response
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// );
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// modport CacheSet(
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// input request,
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// output response
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// );
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// endinterface
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module CacheWithInterface(
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input wire [7:0] dataIn,
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output wire [7:0] dataOut,
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input wire clock, clear
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);
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wire [7:0] myRequest;
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wire [7:0] myResponse;
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// CacheSetInterface dataInterface(
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// .request(myRequest),
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// .response(myResponse)
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// );
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wire [7:0] dataInterface_request;
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wire [7:0] dataInterface_response;
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generate
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assign dataInterface_request = myRequest;
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// dataInterface.myResponse is an output
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assign myResponse = dataInterface_response;
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endgenerate
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CacheSet set(
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.data_request(dataInterface_request),
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.data_response(dataInterface_response),
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.clock(clock),
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.clear(clear)
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);
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assign myRequest = dataIn;
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assign dataOut = myResponse;
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endmodule
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module CacheSet (
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input wire [7:0] data_request,
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output reg [7:0] data_response,
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input wire clock, clear
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);
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always @(posedge clock)
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if(clear)
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data_response <= 8'h0;
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else
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data_response <= ~data_request;
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endmodule
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