mirror of https://github.com/zachjs/sv2v.git
44 lines
1.4 KiB
Systemverilog
44 lines
1.4 KiB
Systemverilog
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`default_nettype none
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module ArrayOrReduction #(
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parameter SIZE = 16, WIDTH=32) (
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input logic [SIZE-1:0][WIDTH-1:0] inputs,
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output logic [WIDTH-1:0] result
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);
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// Recursively generate a pair-wise reduction
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generate
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if(SIZE <= 0) begin : error_case
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DoesNotExit foo();
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end else if (SIZE == 1) begin : base_case_1
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assign result = inputs[0];
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end else if(SIZE == 2) begin : base_case_2
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assign result = inputs[0] | inputs[1];
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end else begin : recursive_case
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logic [1:0][WIDTH-1:0] subResults;
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ArrayOrReduction #(.WIDTH(WIDTH), .SIZE(SIZE/2)) top(.inputs(inputs[SIZE-1:SIZE/2]), .result(subResults[1]));
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ArrayOrReduction #(.WIDTH(WIDTH), .SIZE(SIZE/2)) bot(.inputs(inputs[SIZE/2-1:0]), .result(subResults[0]));
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assign result = subResults[0] | subResults[1];
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end
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endgenerate
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endmodule
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module Array #(parameter ELEMENTS=16, WIDTH=32)(
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// $clog2 is a built in function that does the natural log of 2
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input logic [$clog2(ELEMENTS)-1:0] index,
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input logic [WIDTH-1:0] element,
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output logic [ELEMENTS-1:0][WIDTH-1:0] array,
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input logic clock, clear, enable
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);
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localparam ZERO_ELEMENT = {WIDTH{1'b0}};
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always_ff @(posedge clock)
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if(clear)
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array <= {ELEMENTS{ZERO_ELEMENT}};
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else if(enable)
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array[index] <= element;
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endmodule
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