Files
sv2v/test/error/interface_mismatch_3.sv

11 lines
327 B
Systemverilog
Raw Permalink Normal View History

2021-05-12 21:55:05 -04:00
// pattern: port intf has type Interface1\.ModportB, but the binding intf1\.ModportA has type Interface1\.ModportA
2021-10-07 21:06:45 -06:00
// location: interface_mismatch_3.sv:9:5
2021-05-12 21:55:05 -04:00
`include "interface_mismatch.svh"
module Module(intf);
Interface1.ModportB intf;
endmodule
module top;
Interface1 intf1();
Module m(intf1.ModportA);
endmodule