test/dump/example.sv

module top;
    typedef logic T;
    T x;
    assign x = 1;
endmodule
additional test coverage 2023-05-14 00:54:22 -04:00			`module top;`
replace tabs with spaces in test/dump/example.sv 2023-07-09 14:52:41 -04:00			`typedef logic T;`
			`T x;`
			`assign x = 1;`
additional test coverage 2023-05-14 00:54:22 -04:00			`endmodule`