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19 lines
298 B
Systemverilog
19 lines
298 B
Systemverilog
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package Q;
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localparam W = 5;
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localparam unrelated = 1;
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endpackage
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package P;
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import Q::*;
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export Q::W;
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endpackage
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module Example
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import P::*;
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(
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input logic [W - 1:0] inp
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);
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import Q::unrelated;
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initial $display("%b %0d %0d", inp, $bits(inp), unrelated);
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endmodule
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