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16 lines
256 B
Systemverilog
16 lines
256 B
Systemverilog
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interface Interface(input x);
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initial $display("Hello!");
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endinterface
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module Module(i);
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Interface i;
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initial #1 $display(i.x);
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endmodule
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module top;
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Interface i1();
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Module m1(i1);
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Interface i2(.x());
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Module m2(i2);
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endmodule
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