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16 lines
284 B
Systemverilog
16 lines
284 B
Systemverilog
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interface Interface;
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logic [0:1][0:2] arr;
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endinterface
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module Module(intf);
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Interface intf;
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endmodule
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module top;
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Interface intf();
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Module mod [1][2] (intf);
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assign intf.arr[1] = 6;
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assign intf.arr[0][0] = 1;
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initial $display("%b", intf.arr);
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endmodule
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