mirror of
https://github.com/zachjs/sv2v.git
synced 2026-09-02 02:17:13 +02:00
11 lines
170 B
Verilog
11 lines
170 B
Verilog
|
module top;
|
||
|
|
reg inp;
|
||
|
|
wire out;
|
||
|
|
Example e(inp, out);
|
||
|
|
initial
|
||
|
|
repeat(5) begin
|
||
|
|
#1 inp = 0;
|
||
|
|
#1 inp = 1;
|
||
|
|
end
|
||
|
|
endmodule
|